1. Field of the Invention
This invention relates generally to on-chip testing circuitry for integrated circuits, and more particularly to scan cells utilized in scan testing of integrated circuits.
2. Description of Related Art
To enhance the testability of application specific integrated circuits (ASICs) and to achieve higher fault coverage, a common industry practice is to include scan cells within the integrated circuit that are typically interconnected to form scan chains. While the scan cells permit scan testing, each scan cell requires a finite area on a die and introduces a timing impact on the performance of the integrated circuit. Consequently, the scan cell most commonly used is a muxed-scan cell, which has a small area requirement.
FIG. 1 illustrated a portion of an integrated circuit 100 that includes a plurality of logic blocks 120-A to 120-D and a portion of a scan chain that includes muxed-scan cell 101-A, and muxed-scan cell 101-B. The functions performed by the plurality of logic blocks 120-A to 120-D and the interconnection of logic blocks 120-A to 120-D are not needed to understand the operation of the muxed-scan cells and so are not considered further.
Muxed-scan cell 101-A typically is used to replace a D-type flip-flop. Hence, data output line 110 is connected to data input terminal DI of muxed-scan cell 101-A and data output terminal DQ is connected to logic block 120-A by data input line 117 that provides an input signal to logic block 120-A. Data output terminal DQ of muxed-scan cell 101-A is also connected to scan input terminal SI of next muxed-scan cell 101-B in the scan chain by scan input line 116. Thus, the signal on output terminal DQ of muxed-scan cell drives both lines 116 and 117. Data input terminal DI of muxed-scan cell 101-B is connected to a data output line of logic block 120-A.
A clock line 112 is connected to clock terminal CLK of muxed-scan cell 101-A. The clock signal on clock line 112 is provided to clock terminal CLK of muxed-scan cell 101-B by clock line 118. Notice that in this example, the layout of logic blocks 120-A to 120-D requires a somewhat circuitous routing of clock line 118, which is not uncommon. Each of muxed-scan cells 101-A and 101-B has a scan enable terminal connected to a global scan enable line 114.
Muxed-scan cell 201 (FIG. 2A) is a more detailed illustration of muxed-scan cells 101-A and 101-B. Data input terminal DI and scan input terminal SI are connected-to first and second input terminals of multiplexer 202, respectively. The control terminal of multiplexer 202 is connected to scan enable terminal SE and output line of multiplexer 202 is connected to data input terminal D of D-type flip-flop 203. Output terminal Q of D-type flip-flop 203 is connected to data output terminal DQ of muxed-scan cell 201. Clock terminal CLK of D-type flip-flop 203 is connected to clock terminal CLK of muxed-scan cell 201.
Muxed-scan cell 201 operates in two modes, system mode and scan mode. In system mode, the signal on scan enable terminal SE is held inactive, e.g., tied to ground. Consequently, the signal on data input terminal DI is applied to data input terminal D of D-type flip-flop 203, and clocked into D-type flip-flop 203 by an active edge on terminal CLK. Consequently, in system mode, muxed-scan cell 201 simply functions as a D-type flip-flop. D-type flip-flop 203 works in a conventional manner, and has set-up and hold-time requirements for the signal on input terminal D. As is known to one of skill in the art, the set-up and hold-time requirements are defined with respect to an active edge on clock terminal CLK.
In scan mode, the signal on scan enable terminal SE is driven active so that the signal on scan input terminal SI is passed through multiplexer 202 to data input terminal D of D-type flip-flop 203. Consequently, an active edge on terminal CLK loads the signal on scan input terminal into D-type flip-flop 203 so that the signal is applied to output terminal DQ and in turn to the logic block. This provides controllability. When the signal on scan enable terminal SE is driven inactive, the signal on data input terminal DI from a logic block is passed through multiplexer 202 and is captured in D-type flip-flop 203. This provides observability. Notice that output terminal DQ is used for both the system and scan modes of operation.
While muxed-scan cell 201 requires only an addition of a multiplexer 201 to a D-type flip-flop 203, the interconnection of muxed-scan cells to form a scan chain can result in degradation of the performance of integrated circuit 100 in a system mode, i.e., when the signal on scan enable terminal SE is inactive, and in addition, the scan chain may not function properly in scan mode.
Since output pin DQ of each muxed-scan cell, e.g., cell 101-A, is used for both system and scan modes, output pin DQ of cell 101-A drives both scan input line 116 and data input line 117. When as in FIG. 1, scan input line 116 is considerably longer than data input line 117, scan input line 116 introduces a large capacitance load on output pin DQ. This capacitance is present in system mode, and can cause degradation of the muxed-scan cell""s output signal. Specifically, the output signal can only rise in proportion to the charging of the line capacitance. Since the line capacitance is large, the timing performance is degraded. The timing problems introduced by the capacitance of the scan-input lines are particularly problematic for deep submicron designs, which are dominated by wires.
Another problem introduced by scan input line 116 is that when the data signal on line 110 changes state and is clocked through muxed-scan cell 101-A onto line 117, the signal level also changes on line 116. Thus, the dynamic power dissipation in the system mode is determined not only by the logic circuitry and associated interconnect lines, but also by the total capacitance of the scan input lines of the scan chain. However, in the system mode the scan-input lines have no function, and so the dynamic power consumption of these lines is another parasitic load that must be considered. Thus, the inclusion of a scan chain in an integrated circuit increases the dynamic power requirements in the system mode of operation.
Yet another problem arises in the scan mode. When as illustrated in FIG. 1, scan input line 116 is short relative to clock line 118, the capacitance of clock line 118 is considerably greater than the capacitance of scan input line 116. Consequently, an active clock edge 211 (FIG. 2B) may delayed in reaching terminal CLK of muxed-scan cell 101-B relative to the data signal reaching scan in terminal SI. If the signal (FIG. 2B) on scan in terminal SI of cell 101-B is not stable for hold-time tHOLD after clock edge 211 reaches terminal CLK of cell 101-B, a hold-time violation occurs. As shown in FIG. 2B, the signal on terminal SI falls to zero, prior to the end of hold-time tHOLD. Consequently, the state of the D-type flip-flop in cell 101-B is unknown as a result of the hold-time violation.
Unfortunately, the hold-time violation typically cannot be detected until after the layout is completed. This is considered one of the biggest drawbacks of a scan-chain that utilizes muxed-scan cells.
Hence, while the use of muxed-scan cells in a scan chain enhances the testability and fault coverage of an integrated circuit, these advantages can be obtained only if one is willing to accept the associated penalties. The timing performance is degraded and the dynamic power consumption increased in system mode. In scan mode, hold-time violations can defeat the proper functioning of the scan chain.
According to the principles of this invention, a low power scan cell overcomes the limitations of the prior art muxed-scan cell. When the low power scan cells are included in an integrated circuit, the low power scan cell of this invention eliminates parasitic dynamic power consumption associated with scan circuit lines as well as timing degradations in a system mode of operation. In addition, the low power scan cells of this invention minimize problems with hold-time violations during scan testing. Hence, the low power scan cells of this invention provide all the capability of the prior art muxed-scan cells without any of the associated disadvantages. Consequently, the low power scan cells of this invention can be used to enhance testability and fault coverage in an integrated circuit while the performance of the integrated circuit is enhanced relative to a similar integrated circuit that utilized the prior muxed-scan cells.
In one embodiment of the invention, an integrated circuit includes a lower power scan cell having a data input terminal, a data output terminal, a scan enable terminal, and a scan output terminal. A storage element in the scan cell has a storage element input terminal coupled to the data input terminal and a storage element output terminal coupled to the data output terminal. A propagation delay and isolation element in the scan cell has a first terminal connected to the scan enable terminal, a second terminal coupled to the storage element output terminal, and a third terminal connected to the scan output terminal. A multiplexer in the scan cell has a first input terminal connected to the scan cell data input terminal, a second input terminal connected to a scan input terminal, a control terminal connected to the scan enable terminal, and an output terminal connected to the storage element input terminal.
In one embodiment, the propagation delay and isolation element is an AND gate. The storage element is a D-type flip-flop.
This invention includes a method for enhancing performance of an integrated circuit that includes a scan chain comprised of a plurality of scan cells. The method includes:
connecting only a data output terminal of a scan cell to a data input line of a logic circuit; and
connecting an isolation element to the data output terminal of the scan cell, and to a scan input line wherein dynamic power consumption of the integrated circuit is optimized by isolating the scan input line from the data input line in a system mode of operation of the integrated circuit so that the scan input line does not contribute to the dynamic power consumption. The method of this invention also includes:
selecting a propagation time delay for the isolation element so that an output signal from the scan cell is delayed, in reaching a scan input terminal of another scan cell, a time period that eliminates a hold-time violation.